PCA9685 register map

16-channel 12-bit PWM LED and servo controller with I2C — NXP Semiconductors

76 registers I2C I²C 0x40, 0x41, 0x42, 0x43, 0x44, 0x45, 0x46, 0x47, 0x48, 0x49, 0x4A, 0x4B, 0x4C, 0x4D, 0x4E, 0x4F, 0x50, 0x51, 0x52, 0x53, 0x54, 0x55, 0x56, 0x57, 0x58, 0x59, 0x5A, 0x5B, 0x5C, 0x5D, 0x5E, 0x5F, 0x60, 0x61, 0x62, 0x63, 0x64, 0x65, 0x66, 0x67, 0x68, 0x69, 0x6A, 0x6B, 0x6C, 0x6D, 0x6E, 0x6F, 0x70, 0x71, 0x72, 0x73, 0x74, 0x75, 0x76, 0x77, 0x78, 0x79, 0x7A, 0x7B, 0x7C, 0x7D, 0x7E, 0x7F 8-bit reg addresses 61% bit coverage not yet human-verified

I²C address conflict. On its default address(es) this part collides with ADS1115 (0x48, 0x49, 0x4A, 0x4B); ADXL345 (0x53); BME280 (0x76, 0x77); BMP280 (0x76, 0x77); DS1307 (0x68); DS3231 (0x68); INA219 (0x40, 0x41, 0x42, 0x43, 0x44, 0x45, 0x46, 0x47, 0x48, 0x49, 0x4A, 0x4B, 0x4C, 0x4D, 0x4E, 0x4F); INA226 (0x40, 0x41, 0x42, 0x43, 0x44, 0x45, 0x46, 0x47, 0x48, 0x49, 0x4A, 0x4B, 0x4C, 0x4D, 0x4E, 0x4F); MPU6050 (0x68, 0x69). You cannot put them on the same bus without changing a strap pin, using an I²C multiplexer, or moving one to a second bus. See the full address map.

Get it as a C header

pip install regforge
regforge gen PCA9685 --out ./src --driver --tests

Writes pca9685_regs.h with every address, mask and shift below, a bus-agnostic driver skeleton, and a file of compile-time assertions that make your compiler check the bit arithmetic. No API key needed — this part ships inside the package.

Not yet human-verified. Transcribed and mechanically validated — no overlapping fields, no out-of-range bits, reset values consistent with their fields — but not yet checked line-by-line against the datasheet. Verifying it is a useful half hour.

Registers

Addr	Register	Access	Width	Reset	Description
0x00	MODE1	RW	8	0x11	Mode register 1. Note the reset value: SLEEP is set, so the internal oscillator is off and no PWM is produced until you clear it.
0x01	MODE2	RW	8	0x04	Mode register 2: output drive and inversion
0x02	SUBADR1	RW	8	0xE2	I2C subaddress 1
0x03	SUBADR2	RW	8	0xE4	I2C subaddress 2
0x04	SUBADR3	RW	8	0xE8	I2C subaddress 3
0x05	ALLCALLADR	RW	8	0xE0	LED All Call I2C address
0x06	LED0_ON_L	RW	8	0x00	Channel 0 turn-on count, bits [7:0]
0x07	LED0_ON_H	RW	8	0x00	Channel 0 turn-on count bits [11:8], plus the full-ON bit
0x08	LED0_OFF_L	RW	8	0x00	Channel 0 turn-off count, bits [7:0]
0x09	LED0_OFF_H	RW	8	0x00	Channel 0 turn-off count bits [11:8], plus the full-OFF bit
0x0A	LED1_ON_L	RW	8	0x00	Channel 1 turn-on count, bits [7:0]
0x0B	LED1_ON_H	RW	8	0x00	Channel 1 turn-on count bits [11:8], plus the full-ON bit
0x0C	LED1_OFF_L	RW	8	0x00	Channel 1 turn-off count, bits [7:0]
0x0D	LED1_OFF_H	RW	8	0x00	Channel 1 turn-off count bits [11:8], plus the full-OFF bit
0x0E	LED2_ON_L	RW	8	0x00	Channel 2 turn-on count, bits [7:0]
0x0F	LED2_ON_H	RW	8	0x00	Channel 2 turn-on count bits [11:8], plus the full-ON bit
0x10	LED2_OFF_L	RW	8	0x00	Channel 2 turn-off count, bits [7:0]
0x11	LED2_OFF_H	RW	8	0x00	Channel 2 turn-off count bits [11:8], plus the full-OFF bit
0x12	LED3_ON_L	RW	8	0x00	Channel 3 turn-on count, bits [7:0]
0x13	LED3_ON_H	RW	8	0x00	Channel 3 turn-on count bits [11:8], plus the full-ON bit
0x14	LED3_OFF_L	RW	8	0x00	Channel 3 turn-off count, bits [7:0]
0x15	LED3_OFF_H	RW	8	0x00	Channel 3 turn-off count bits [11:8], plus the full-OFF bit
0x16	LED4_ON_L	RW	8	0x00	Channel 4 turn-on count, bits [7:0]
0x17	LED4_ON_H	RW	8	0x00	Channel 4 turn-on count bits [11:8], plus the full-ON bit
0x18	LED4_OFF_L	RW	8	0x00	Channel 4 turn-off count, bits [7:0]
0x19	LED4_OFF_H	RW	8	0x00	Channel 4 turn-off count bits [11:8], plus the full-OFF bit
0x1A	LED5_ON_L	RW	8	0x00	Channel 5 turn-on count, bits [7:0]
0x1B	LED5_ON_H	RW	8	0x00	Channel 5 turn-on count bits [11:8], plus the full-ON bit
0x1C	LED5_OFF_L	RW	8	0x00	Channel 5 turn-off count, bits [7:0]
0x1D	LED5_OFF_H	RW	8	0x00	Channel 5 turn-off count bits [11:8], plus the full-OFF bit
0x1E	LED6_ON_L	RW	8	0x00	Channel 6 turn-on count, bits [7:0]
0x1F	LED6_ON_H	RW	8	0x00	Channel 6 turn-on count bits [11:8], plus the full-ON bit
0x20	LED6_OFF_L	RW	8	0x00	Channel 6 turn-off count, bits [7:0]
0x21	LED6_OFF_H	RW	8	0x00	Channel 6 turn-off count bits [11:8], plus the full-OFF bit
0x22	LED7_ON_L	RW	8	0x00	Channel 7 turn-on count, bits [7:0]
0x23	LED7_ON_H	RW	8	0x00	Channel 7 turn-on count bits [11:8], plus the full-ON bit
0x24	LED7_OFF_L	RW	8	0x00	Channel 7 turn-off count, bits [7:0]
0x25	LED7_OFF_H	RW	8	0x00	Channel 7 turn-off count bits [11:8], plus the full-OFF bit
0x26	LED8_ON_L	RW	8	0x00	Channel 8 turn-on count, bits [7:0]
0x27	LED8_ON_H	RW	8	0x00	Channel 8 turn-on count bits [11:8], plus the full-ON bit
0x28	LED8_OFF_L	RW	8	0x00	Channel 8 turn-off count, bits [7:0]
0x29	LED8_OFF_H	RW	8	0x00	Channel 8 turn-off count bits [11:8], plus the full-OFF bit
0x2A	LED9_ON_L	RW	8	0x00	Channel 9 turn-on count, bits [7:0]
0x2B	LED9_ON_H	RW	8	0x00	Channel 9 turn-on count bits [11:8], plus the full-ON bit
0x2C	LED9_OFF_L	RW	8	0x00	Channel 9 turn-off count, bits [7:0]
0x2D	LED9_OFF_H	RW	8	0x00	Channel 9 turn-off count bits [11:8], plus the full-OFF bit
0x2E	LED10_ON_L	RW	8	0x00	Channel 10 turn-on count, bits [7:0]
0x2F	LED10_ON_H	RW	8	0x00	Channel 10 turn-on count bits [11:8], plus the full-ON bit
0x30	LED10_OFF_L	RW	8	0x00	Channel 10 turn-off count, bits [7:0]
0x31	LED10_OFF_H	RW	8	0x00	Channel 10 turn-off count bits [11:8], plus the full-OFF bit
0x32	LED11_ON_L	RW	8	0x00	Channel 11 turn-on count, bits [7:0]
0x33	LED11_ON_H	RW	8	0x00	Channel 11 turn-on count bits [11:8], plus the full-ON bit
0x34	LED11_OFF_L	RW	8	0x00	Channel 11 turn-off count, bits [7:0]
0x35	LED11_OFF_H	RW	8	0x00	Channel 11 turn-off count bits [11:8], plus the full-OFF bit
0x36	LED12_ON_L	RW	8	0x00	Channel 12 turn-on count, bits [7:0]
0x37	LED12_ON_H	RW	8	0x00	Channel 12 turn-on count bits [11:8], plus the full-ON bit
0x38	LED12_OFF_L	RW	8	0x00	Channel 12 turn-off count, bits [7:0]
0x39	LED12_OFF_H	RW	8	0x00	Channel 12 turn-off count bits [11:8], plus the full-OFF bit
0x3A	LED13_ON_L	RW	8	0x00	Channel 13 turn-on count, bits [7:0]
0x3B	LED13_ON_H	RW	8	0x00	Channel 13 turn-on count bits [11:8], plus the full-ON bit
0x3C	LED13_OFF_L	RW	8	0x00	Channel 13 turn-off count, bits [7:0]
0x3D	LED13_OFF_H	RW	8	0x00	Channel 13 turn-off count bits [11:8], plus the full-OFF bit
0x3E	LED14_ON_L	RW	8	0x00	Channel 14 turn-on count, bits [7:0]
0x3F	LED14_ON_H	RW	8	0x00	Channel 14 turn-on count bits [11:8], plus the full-ON bit
0x40	LED14_OFF_L	RW	8	0x00	Channel 14 turn-off count, bits [7:0]
0x41	LED14_OFF_H	RW	8	0x00	Channel 14 turn-off count bits [11:8], plus the full-OFF bit
0x42	LED15_ON_L	RW	8	0x00	Channel 15 turn-on count, bits [7:0]
0x43	LED15_ON_H	RW	8	0x00	Channel 15 turn-on count bits [11:8], plus the full-ON bit
0x44	LED15_OFF_L	RW	8	0x00	Channel 15 turn-off count, bits [7:0]
0x45	LED15_OFF_H	RW	8	0x00	Channel 15 turn-off count bits [11:8], plus the full-OFF bit
0xFA	ALL_LED_ON_L	WO	8	—	Turn-on count for all channels, bits [7:0]
0xFB	ALL_LED_ON_H	WO	8	—	Turn-on count for all channels, bits [11:8] and full-ON
0xFC	ALL_LED_OFF_L	WO	8	—	Turn-off count for all channels, bits [7:0]
0xFD	ALL_LED_OFF_H	WO	8	—	Turn-off count for all channels, bits [11:8] and full-OFF
0xFE	PRESCALE	RW	8	0x1E	PWM frequency prescaler. Writable only while MODE1.SLEEP is set. prescale = round(osc_clock / (4096 * pwm_freq)) - 1; the 0x1E default is 200 Hz with the internal 25 MHz oscillator.
0xFF	TESTMODE	RW	8	—	Factory test mode. Do not write.

Bit layouts

Drawn MSB-first, the way the datasheet draws them. [7:5] means shift 5, width 3, mask 0xE0 — this is the notation that costs people a day when they read it backwards.

MODE1 @ 0x00 — 8 fields

RESTART[7]

EXTCLK[6]

AI[5]

SLEEP[4]

SUB1[3]

SUB2[2]

SUB3[1]

ALLCALL[0]

Bits	Field	Access	Mask	Reset	Description
[7]	RESTART	RW1C	0x80	0x00	Reads 1 when a restart is required; write 1 to clear
[6]	EXTCLK	RW	0x40	0x00	Use an external clock. Sticky until power cycle or SWRST.
[5]	AI	RW	0x20	0x00	Register auto-increment enable
[4]	SLEEP	RW	0x10	0x01	Low-power mode, oscillator off. Set at reset.
[3]	SUB1	RW	0x08	0x00	Respond to I2C subaddress 1
[2]	SUB2	RW	0x04	0x00	Respond to I2C subaddress 2
[1]	SUB3	RW	0x02	0x00	Respond to I2C subaddress 3
[0]	ALLCALL	RW	0x01	0x01	Respond to the LED All Call address

MODE2 @ 0x01 — 4 fields

—7

—6

—5

INVRT[4]

OCH[3]

OUTDRV[2]

OUTNE[1:0]

Bits	Field	Access	Mask	Reset	Description
[4]	INVRT	RW	0x10	0x00	Invert the output logic state
[3]	OCH	RW	0x08	0x00	0 = outputs change on STOP, 1 = on ACK
[2]	OUTDRV	RW	0x04	0x01	0 = open drain, 1 = totem pole
[1:0]	OUTNE	RW	0x03	0x00	Output state when OE is high

MODE2.OUTNE values

Value	Name	Meaning
0x00	LOW	Outputs go low
0x01	OUTDRV_DEPENDENT	High if OUTDRV=1, otherwise high-impedance
0x02	HIGH_Z	Outputs go high-impedance

LED0_ON_H @ 0x07 — 2 fields

—7

—6

—5

FULL_ON[4]

ON_COUNT_H[3:0]

Bits	Field	Access	Mask	Reset	Description
[4]	FULL_ON	RW	0x10	0x00	Drive the output permanently high
[3:0]	ON_COUNT_H	RW	0x0F	0x00	Turn-on count, bits [11:8]

LED0_OFF_H @ 0x09 — 2 fields

—7

—6

—5

FULL_OFF[4]

OFF_COUNT_H[3:0]

Bits	Field	Access	Mask	Reset	Description
[4]	FULL_OFF	RW	0x10	0x00	Drive the output permanently low. Takes priority over FULL_ON.
[3:0]	OFF_COUNT_H	RW	0x0F	0x00	Turn-off count, bits [11:8]

LED1_ON_H @ 0x0B — 2 fields

—7

—6

—5

FULL_ON[4]

ON_COUNT_H[3:0]

Bits	Field	Access	Mask	Reset	Description
[4]	FULL_ON	RW	0x10	0x00	Drive the output permanently high
[3:0]	ON_COUNT_H	RW	0x0F	0x00	Turn-on count, bits [11:8]

LED1_OFF_H @ 0x0D — 2 fields

—7

—6

—5

FULL_OFF[4]

OFF_COUNT_H[3:0]

Bits	Field	Access	Mask	Reset	Description
[4]	FULL_OFF	RW	0x10	0x00	Drive the output permanently low. Takes priority over FULL_ON.
[3:0]	OFF_COUNT_H	RW	0x0F	0x00	Turn-off count, bits [11:8]

LED2_ON_H @ 0x0F — 2 fields

—7

—6

—5

FULL_ON[4]

ON_COUNT_H[3:0]

Bits	Field	Access	Mask	Reset	Description
[4]	FULL_ON	RW	0x10	0x00	Drive the output permanently high
[3:0]	ON_COUNT_H	RW	0x0F	0x00	Turn-on count, bits [11:8]

LED2_OFF_H @ 0x11 — 2 fields

—7

—6

—5

FULL_OFF[4]

OFF_COUNT_H[3:0]

Bits	Field	Access	Mask	Reset	Description
[4]	FULL_OFF	RW	0x10	0x00	Drive the output permanently low. Takes priority over FULL_ON.
[3:0]	OFF_COUNT_H	RW	0x0F	0x00	Turn-off count, bits [11:8]

LED3_ON_H @ 0x13 — 2 fields

—7

—6

—5

FULL_ON[4]

ON_COUNT_H[3:0]

Bits	Field	Access	Mask	Reset	Description
[4]	FULL_ON	RW	0x10	0x00	Drive the output permanently high
[3:0]	ON_COUNT_H	RW	0x0F	0x00	Turn-on count, bits [11:8]

LED3_OFF_H @ 0x15 — 2 fields

—7

—6

—5

FULL_OFF[4]

OFF_COUNT_H[3:0]

Bits	Field	Access	Mask	Reset	Description
[4]	FULL_OFF	RW	0x10	0x00	Drive the output permanently low. Takes priority over FULL_ON.
[3:0]	OFF_COUNT_H	RW	0x0F	0x00	Turn-off count, bits [11:8]

LED4_ON_H @ 0x17 — 2 fields

—7

—6

—5

FULL_ON[4]

ON_COUNT_H[3:0]

Bits	Field	Access	Mask	Reset	Description
[4]	FULL_ON	RW	0x10	0x00	Drive the output permanently high
[3:0]	ON_COUNT_H	RW	0x0F	0x00	Turn-on count, bits [11:8]

LED4_OFF_H @ 0x19 — 2 fields

—7

—6

—5

FULL_OFF[4]

OFF_COUNT_H[3:0]

Bits	Field	Access	Mask	Reset	Description
[4]	FULL_OFF	RW	0x10	0x00	Drive the output permanently low. Takes priority over FULL_ON.
[3:0]	OFF_COUNT_H	RW	0x0F	0x00	Turn-off count, bits [11:8]

LED5_ON_H @ 0x1B — 2 fields

—7

—6

—5

FULL_ON[4]

ON_COUNT_H[3:0]

Bits	Field	Access	Mask	Reset	Description
[4]	FULL_ON	RW	0x10	0x00	Drive the output permanently high
[3:0]	ON_COUNT_H	RW	0x0F	0x00	Turn-on count, bits [11:8]

LED5_OFF_H @ 0x1D — 2 fields

—7

—6

—5

FULL_OFF[4]

OFF_COUNT_H[3:0]

Bits	Field	Access	Mask	Reset	Description
[4]	FULL_OFF	RW	0x10	0x00	Drive the output permanently low. Takes priority over FULL_ON.
[3:0]	OFF_COUNT_H	RW	0x0F	0x00	Turn-off count, bits [11:8]

LED6_ON_H @ 0x1F — 2 fields

—7

—6

—5

FULL_ON[4]

ON_COUNT_H[3:0]

Bits	Field	Access	Mask	Reset	Description
[4]	FULL_ON	RW	0x10	0x00	Drive the output permanently high
[3:0]	ON_COUNT_H	RW	0x0F	0x00	Turn-on count, bits [11:8]

LED6_OFF_H @ 0x21 — 2 fields

—7

—6

—5

FULL_OFF[4]

OFF_COUNT_H[3:0]

Bits	Field	Access	Mask	Reset	Description
[4]	FULL_OFF	RW	0x10	0x00	Drive the output permanently low. Takes priority over FULL_ON.
[3:0]	OFF_COUNT_H	RW	0x0F	0x00	Turn-off count, bits [11:8]

LED7_ON_H @ 0x23 — 2 fields

—7

—6

—5

FULL_ON[4]

ON_COUNT_H[3:0]

Bits	Field	Access	Mask	Reset	Description
[4]	FULL_ON	RW	0x10	0x00	Drive the output permanently high
[3:0]	ON_COUNT_H	RW	0x0F	0x00	Turn-on count, bits [11:8]

LED7_OFF_H @ 0x25 — 2 fields

—7

—6

—5

FULL_OFF[4]

OFF_COUNT_H[3:0]

Bits	Field	Access	Mask	Reset	Description
[4]	FULL_OFF	RW	0x10	0x00	Drive the output permanently low. Takes priority over FULL_ON.
[3:0]	OFF_COUNT_H	RW	0x0F	0x00	Turn-off count, bits [11:8]

LED8_ON_H @ 0x27 — 2 fields

—7

—6

—5

FULL_ON[4]

ON_COUNT_H[3:0]

Bits	Field	Access	Mask	Reset	Description
[4]	FULL_ON	RW	0x10	0x00	Drive the output permanently high
[3:0]	ON_COUNT_H	RW	0x0F	0x00	Turn-on count, bits [11:8]

LED8_OFF_H @ 0x29 — 2 fields

—7

—6

—5

FULL_OFF[4]

OFF_COUNT_H[3:0]

Bits	Field	Access	Mask	Reset	Description
[4]	FULL_OFF	RW	0x10	0x00	Drive the output permanently low. Takes priority over FULL_ON.
[3:0]	OFF_COUNT_H	RW	0x0F	0x00	Turn-off count, bits [11:8]

LED9_ON_H @ 0x2B — 2 fields

—7

—6

—5

FULL_ON[4]

ON_COUNT_H[3:0]

Bits	Field	Access	Mask	Reset	Description
[4]	FULL_ON	RW	0x10	0x00	Drive the output permanently high
[3:0]	ON_COUNT_H	RW	0x0F	0x00	Turn-on count, bits [11:8]

LED9_OFF_H @ 0x2D — 2 fields

—7

—6

—5

FULL_OFF[4]

OFF_COUNT_H[3:0]

Bits	Field	Access	Mask	Reset	Description
[4]	FULL_OFF	RW	0x10	0x00	Drive the output permanently low. Takes priority over FULL_ON.
[3:0]	OFF_COUNT_H	RW	0x0F	0x00	Turn-off count, bits [11:8]

LED10_ON_H @ 0x2F — 2 fields

—7

—6

—5

FULL_ON[4]

ON_COUNT_H[3:0]

Bits	Field	Access	Mask	Reset	Description
[4]	FULL_ON	RW	0x10	0x00	Drive the output permanently high
[3:0]	ON_COUNT_H	RW	0x0F	0x00	Turn-on count, bits [11:8]

LED10_OFF_H @ 0x31 — 2 fields

—7

—6

—5

FULL_OFF[4]

OFF_COUNT_H[3:0]

Bits	Field	Access	Mask	Reset	Description
[4]	FULL_OFF	RW	0x10	0x00	Drive the output permanently low. Takes priority over FULL_ON.
[3:0]	OFF_COUNT_H	RW	0x0F	0x00	Turn-off count, bits [11:8]

LED11_ON_H @ 0x33 — 2 fields

—7

—6

—5

FULL_ON[4]

ON_COUNT_H[3:0]

Bits	Field	Access	Mask	Reset	Description
[4]	FULL_ON	RW	0x10	0x00	Drive the output permanently high
[3:0]	ON_COUNT_H	RW	0x0F	0x00	Turn-on count, bits [11:8]

LED11_OFF_H @ 0x35 — 2 fields

—7

—6

—5

FULL_OFF[4]

OFF_COUNT_H[3:0]

Bits	Field	Access	Mask	Reset	Description
[4]	FULL_OFF	RW	0x10	0x00	Drive the output permanently low. Takes priority over FULL_ON.
[3:0]	OFF_COUNT_H	RW	0x0F	0x00	Turn-off count, bits [11:8]

LED12_ON_H @ 0x37 — 2 fields

—7

—6

—5

FULL_ON[4]

ON_COUNT_H[3:0]

Bits	Field	Access	Mask	Reset	Description
[4]	FULL_ON	RW	0x10	0x00	Drive the output permanently high
[3:0]	ON_COUNT_H	RW	0x0F	0x00	Turn-on count, bits [11:8]

LED12_OFF_H @ 0x39 — 2 fields

—7

—6

—5

FULL_OFF[4]

OFF_COUNT_H[3:0]

Bits	Field	Access	Mask	Reset	Description
[4]	FULL_OFF	RW	0x10	0x00	Drive the output permanently low. Takes priority over FULL_ON.
[3:0]	OFF_COUNT_H	RW	0x0F	0x00	Turn-off count, bits [11:8]

LED13_ON_H @ 0x3B — 2 fields

—7

—6

—5

FULL_ON[4]

ON_COUNT_H[3:0]

Bits	Field	Access	Mask	Reset	Description
[4]	FULL_ON	RW	0x10	0x00	Drive the output permanently high
[3:0]	ON_COUNT_H	RW	0x0F	0x00	Turn-on count, bits [11:8]

LED13_OFF_H @ 0x3D — 2 fields

—7

—6

—5

FULL_OFF[4]

OFF_COUNT_H[3:0]

Bits	Field	Access	Mask	Reset	Description
[4]	FULL_OFF	RW	0x10	0x00	Drive the output permanently low. Takes priority over FULL_ON.
[3:0]	OFF_COUNT_H	RW	0x0F	0x00	Turn-off count, bits [11:8]

LED14_ON_H @ 0x3F — 2 fields

—7

—6

—5

FULL_ON[4]

ON_COUNT_H[3:0]

Bits	Field	Access	Mask	Reset	Description
[4]	FULL_ON	RW	0x10	0x00	Drive the output permanently high
[3:0]	ON_COUNT_H	RW	0x0F	0x00	Turn-on count, bits [11:8]

LED14_OFF_H @ 0x41 — 2 fields

—7

—6

—5

FULL_OFF[4]

OFF_COUNT_H[3:0]

Bits	Field	Access	Mask	Reset	Description
[4]	FULL_OFF	RW	0x10	0x00	Drive the output permanently low. Takes priority over FULL_ON.
[3:0]	OFF_COUNT_H	RW	0x0F	0x00	Turn-off count, bits [11:8]

LED15_ON_H @ 0x43 — 2 fields

—7

—6

—5

FULL_ON[4]

ON_COUNT_H[3:0]

Bits	Field	Access	Mask	Reset	Description
[4]	FULL_ON	RW	0x10	0x00	Drive the output permanently high
[3:0]	ON_COUNT_H	RW	0x0F	0x00	Turn-on count, bits [11:8]

LED15_OFF_H @ 0x45 — 2 fields

—7

—6

—5

FULL_OFF[4]

OFF_COUNT_H[3:0]

Bits	Field	Access	Mask	Reset	Description
[4]	FULL_OFF	RW	0x10	0x00	Drive the output permanently low. Takes priority over FULL_ON.
[3:0]	OFF_COUNT_H	RW	0x0F	0x00	Turn-off count, bits [11:8]

ALL_LED_ON_H @ 0xFB — 1 fields

—7

—6

—5

FULL_ON[4]

—3

—2

—1

—0

Bits	Field	Access	Mask	Reset	Description
[4]	FULL_ON	WO	0x10	—	Drive all outputs permanently high

ALL_LED_OFF_H @ 0xFD — 1 fields

—7

—6

—5

FULL_OFF[4]

—3

—2

—1

—0

Bits	Field	Access	Mask	Reset	Description
[4]	FULL_OFF	WO	0x10	—	Drive all outputs permanently low

Generated C header

What regforge gen PCA9685 writes for MODE1:

/* ------------------------------------------------------------------------ */
/* MODE1 @ 0x00u  rw  8-bit  reset 0x11u */
/* Mode register 1. Note the reset value: SLEEP is set, so the internal oscillator is off and no PWM is produced until you clear it. */
/* ------------------------------------------------------------------------ */

#define PCA9685_MODE1                                  0x00u
#define PCA9685_MODE1_WIDTH                            8u
#define PCA9685_MODE1_RESET                            0x11u

/*   RESTART bits [7] rw1c reset 0x00u -- Reads 1 when a restart is required; write 1 to clear */
#define PCA9685_MODE1_RESTART_SHIFT                    7u
#define PCA9685_MODE1_RESTART_WIDTH                    1u
#define PCA9685_MODE1_RESTART_MASK                     0x80u
#define PCA9685_MODE1_RESTART_GET(reg)                 (((uint8_t)(reg) & 0x80u) >> 7u)
#define PCA9685_MODE1_RESTART_SET(reg, val)            (((uint8_t)(reg) & (uint8_t)~0x80u) | (((uint8_t)(val) << 7u) & 0x80u))

/*   EXTCLK bits [6] rw reset 0x00u -- Use an external clock. Sticky until power cycle or SWRST. */
#define PCA9685_MODE1_EXTCLK_SHIFT                     6u
#define PCA9685_MODE1_EXTCLK_WIDTH                     1u
#define PCA9685_MODE1_EXTCLK_MASK                      0x40u
#define PCA9685_MODE1_EXTCLK_GET(reg)                  (((uint8_t)(reg) & 0x40u) >> 6u)
#define PCA9685_MODE1_EXTCLK_SET(reg, val)             (((uint8_t)(reg) & (uint8_t)~0x40u) | (((uint8_t)(val) << 6u) & 0x40u))

/*   AI bits [5] rw reset 0x00u -- Register auto-increment enable */
#define PCA9685_MODE1_AI_SHIFT                         5u
#define PCA9685_MODE1_AI_WIDTH                         1u
#define PCA9685_MODE1_AI_MASK                          0x20u
#define PCA9685_MODE1_AI_GET(reg)                      (((uint8_t)(reg) & 0x20u) >> 5u)
#define PCA9685_MODE1_AI_SET(reg, val)                 (((uint8_t)(reg) & (uint8_t)~0x20u) | (((uint8_t)(val) << 5u) & 0x20u))

/*   SLEEP bits [4] rw reset 0x01u -- Low-power mode, oscillator off. Set at reset. */
#define PCA9685_MODE1_SLEEP_SHIFT                      4u
#define PCA9685_MODE1_SLEEP_WIDTH                      1u
#define PCA9685_MODE1_SLEEP_MASK                       0x10u
#define PCA9685_MODE1_SLEEP_GET(reg)                   (((uint8_t)(reg) & 0x10u) >> 4u)
#define PCA9685_MODE1_SLEEP_SET(reg, val)              (((uint8_t)(reg) & (uint8_t)~0x10u) | (((uint8_t)(val) << 4u) & 0x10u))

/*   SUB1 bits [3] rw reset 0x00u -- Respond to I2C subaddress 1 */
#define PCA9685_MODE1_SUB1_SHIFT                       3u
#define PCA9685_MODE1_SUB1_WIDTH                       1u
#define PCA9685_MODE1_SUB1_MASK                        0x08u
#define PCA9685_MODE1_SUB1_GET(reg)                    (((uint8_t)(reg) & 0x08u) >> 3u)
#define PCA9685_MODE1_SUB1_SET(reg, val)               (((uint8_t)(reg) & (uint8_t)~0x08u) | (((uint8_t)(val) << 3u) & 0x08u))

Related parts

Source

Transcribed from NXP PCA9685 datasheet (hand-transcribed) (hand-transcribed). Hand-authored seed entry, not machine-extracted. The 64 per-channel LED registers are generated programmatically from the documented 4-per-channel layout starting at 0x06. Check against the datasheet before trusting it, then mark it verified.

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