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ADXL345 register map

3-axis MEMS accelerometer with tap, activity and free-fall detection — Analog Devices

30 registers I2C, SPI I²C 0x53, 0x1D 8-bit reg addresses 86% bit coverage not yet human-verified
I²C address conflict. On its default address(es) this part collides with PCA9685 (0x53). You cannot put them on the same bus without changing a strap pin, using an I²C multiplexer, or moving one to a second bus. See the full address map.

Get it as a C header

pip install regforge
regforge gen ADXL345 --out ./src --driver --tests

Writes adxl345_regs.h with every address, mask and shift below, a bus-agnostic driver skeleton, and a file of compile-time assertions that make your compiler check the bit arithmetic. No API key needed — this part ships inside the package.

Not yet human-verified. Transcribed and mechanically validated — no overlapping fields, no out-of-range bits, reset values consistent with their fields — but not yet checked line-by-line against the datasheet. Verifying it is a useful half hour.

Registers

AddrRegisterAccessWidthResetDescription
0x00DEVIDRO80xE5Device ID. Always reads 0xE5.
0x1DTHRESH_TAPRW8—Tap threshold, 62.5 mg per LSB
0x1EOFSXRW8—X-axis offset, two's complement, 15.6 mg per LSB
0x1FOFSYRW8—Y-axis offset, two's complement, 15.6 mg per LSB
0x20OFSZRW8—Z-axis offset, two's complement, 15.6 mg per LSB
0x21DURRW8—Maximum tap duration, 625 us per LSB
0x22LATENTRW8—Tap latency, 1.25 ms per LSB
0x23WINDOWRW8—Double-tap window, 1.25 ms per LSB
0x24THRESH_ACTRW8—Activity threshold, 62.5 mg per LSB
0x25THRESH_INACTRW8—Inactivity threshold, 62.5 mg per LSB
0x26TIME_INACTRW8—Inactivity time, 1 s per LSB
0x27ACT_INACT_CTLRW80x00Axis enables for activity and inactivity detection
0x28THRESH_FFRW8—Free-fall threshold, 62.5 mg per LSB
0x29TIME_FFRW8—Free-fall time, 5 ms per LSB
0x2ATAP_AXESRW80x00Axis enables for tap detection
0x2BACT_TAP_STATUSRO80x00Which axis was involved in the most recent event
0x2CBW_RATERW80x0AOutput data rate and low-power mode
0x2DPOWER_CTLRW80x00Power-saving control. Measure is clear at reset, so the part boots in standby and produces no data until you set it.
0x2EINT_ENABLERW80x00Interrupt enables
0x2FINT_MAPRW80x00Interrupt routing. 0 sends the event to INT1, 1 sends it to INT2.
0x30INT_SOURCERO80x02Which interrupts are asserted. Reading clears most of them.
0x31DATA_FORMATRW80x00Data presentation. FULL_RES changes how the 13-bit result is aligned, which is the usual cause of scaling that looks wrong by a factor of 2.
0x32DATAX0RO8—X-axis measurement, low byte
0x33DATAX1RO8—X-axis measurement, high byte
0x34DATAY0RO8—Y-axis measurement, low byte
0x35DATAY1RO8—Y-axis measurement, high byte
0x36DATAZ0RO8—Z-axis measurement, low byte
0x37DATAZ1RO8—Z-axis measurement, high byte
0x38FIFO_CTLRW80x00FIFO mode and watermark
0x39FIFO_STATUSRO80x00FIFO fill level

Bit layouts

Drawn MSB-first, the way the datasheet draws them. [7:5] means shift 5, width 3, mask 0xE0 — this is the notation that costs people a day when they read it backwards.

ACT_INACT_CTL  @  0x27  —  8 fields
ACT_AC_DC[7]
ACT_X_EN[6]
ACT_Y_EN[5]
ACT_Z_EN[4]
INACT_AC_DC[3]
INACT_X_EN[2]
INACT_Y_EN[1]
INACT_Z_EN[0]
BitsFieldAccessMaskResetDescription
[7]ACT_AC_DCRW0x800x00Activity: 0 = dc-coupled, 1 = ac-coupled
[6]ACT_X_ENRW0x400x00Enable X for activity
[5]ACT_Y_ENRW0x200x00Enable Y for activity
[4]ACT_Z_ENRW0x100x00Enable Z for activity
[3]INACT_AC_DCRW0x080x00Inactivity: 0 = dc-coupled, 1 = ac-coupled
[2]INACT_X_ENRW0x040x00Enable X for inactivity
[1]INACT_Y_ENRW0x020x00Enable Y for inactivity
[0]INACT_Z_ENRW0x010x00Enable Z for inactivity
TAP_AXES  @  0x2A  —  4 fields
—7
—6
—5
—4
SUPPRESS[3]
TAP_X_EN[2]
TAP_Y_EN[1]
TAP_Z_EN[0]
BitsFieldAccessMaskResetDescription
[3]SUPPRESSRW0x080x00Suppress double tap if a spike occurs during latency
[2]TAP_X_ENRW0x040x00Enable X for tap
[1]TAP_Y_ENRW0x020x00Enable Y for tap
[0]TAP_Z_ENRW0x010x00Enable Z for tap
ACT_TAP_STATUS  @  0x2B  —  7 fields
—7
ACT_X_SRC[6]
ACT_Y_SRC[5]
ACT_Z_SRC[4]
ASLEEP[3]
TAP_X_SRC[2]
TAP_Y_SRC[1]
TAP_Z_SRC[0]
BitsFieldAccessMaskResetDescription
[6]ACT_X_SRCRO0x400x00X involved in activity
[5]ACT_Y_SRCRO0x200x00Y involved in activity
[4]ACT_Z_SRCRO0x100x00Z involved in activity
[3]ASLEEPRO0x080x00Device is in sleep mode
[2]TAP_X_SRCRO0x040x00X involved in tap
[1]TAP_Y_SRCRO0x020x00Y involved in tap
[0]TAP_Z_SRCRO0x010x00Z involved in tap
BW_RATE  @  0x2C  —  2 fields
—7
—6
—5
LOW_POWER[4]
RATE[3:0]
BitsFieldAccessMaskResetDescription
[4]LOW_POWERRW0x100x00Reduced power at the cost of higher noise
[3:0]RATERW0x0F0x0AOutput data rate

BW_RATE.RATE values

ValueNameMeaning
0x00HZ_0_100.10 Hz
0x01HZ_0_200.20 Hz
0x02HZ_0_390.39 Hz
0x03HZ_0_780.78 Hz
0x04HZ_1_561.56 Hz
0x05HZ_3_133.13 Hz
0x06HZ_6_256.25 Hz
0x07HZ_12_512.5 Hz
0x08HZ_2525 Hz
0x09HZ_5050 Hz
0x0AHZ_100100 Hz (default)
0x0BHZ_200200 Hz
0x0CHZ_400400 Hz
0x0DHZ_800800 Hz
0x0EHZ_16001600 Hz
0x0FHZ_32003200 Hz
POWER_CTL  @  0x2D  —  5 fields
—7
—6
LINK[5]
AUTO_SLEEP[4]
MEASURE[3]
SLEEP[2]
WAKEUP[1:0]
BitsFieldAccessMaskResetDescription
[5]LINKRW0x200x00Serially link activity and inactivity detection
[4]AUTO_SLEEPRW0x100x00Enter sleep automatically on inactivity
[3]MEASURERW0x080x000 = standby, 1 = measurement. Set this to start.
[2]SLEEPRW0x040x00Put the part into sleep mode
[1:0]WAKEUPRW0x030x00Reading rate in sleep mode

POWER_CTL.WAKEUP values

ValueNameMeaning
0x00HZ_88 Hz
0x01HZ_44 Hz
0x02HZ_22 Hz
0x03HZ_11 Hz
INT_ENABLE  @  0x2E  —  8 fields
DATA_READY[7]
SINGLE_TAP[6]
DOUBLE_TAP[5]
ACTIVITY[4]
INACTIVITY[3]
FREE_FALL[2]
WATERMARK[1]
OVERRUN[0]
BitsFieldAccessMaskResetDescription
[7]DATA_READYRW0x800x00Data ready
[6]SINGLE_TAPRW0x400x00Single tap
[5]DOUBLE_TAPRW0x200x00Double tap
[4]ACTIVITYRW0x100x00Activity
[3]INACTIVITYRW0x080x00Inactivity
[2]FREE_FALLRW0x040x00Free fall
[1]WATERMARKRW0x020x00FIFO watermark
[0]OVERRUNRW0x010x00FIFO overrun
INT_MAP  @  0x2F  —  8 fields
DATA_READY[7]
SINGLE_TAP[6]
DOUBLE_TAP[5]
ACTIVITY[4]
INACTIVITY[3]
FREE_FALL[2]
WATERMARK[1]
OVERRUN[0]
BitsFieldAccessMaskResetDescription
[7]DATA_READYRW0x800x00Route data ready
[6]SINGLE_TAPRW0x400x00Route single tap
[5]DOUBLE_TAPRW0x200x00Route double tap
[4]ACTIVITYRW0x100x00Route activity
[3]INACTIVITYRW0x080x00Route inactivity
[2]FREE_FALLRW0x040x00Route free fall
[1]WATERMARKRW0x020x00Route FIFO watermark
[0]OVERRUNRW0x010x00Route FIFO overrun
INT_SOURCE  @  0x30  —  8 fields
DATA_READY[7]
SINGLE_TAP[6]
DOUBLE_TAP[5]
ACTIVITY[4]
INACTIVITY[3]
FREE_FALL[2]
WATERMARK[1]
OVERRUN[0]
BitsFieldAccessMaskResetDescription
[7]DATA_READYRO0x800x00Data ready
[6]SINGLE_TAPRO0x400x00Single tap
[5]DOUBLE_TAPRO0x200x00Double tap
[4]ACTIVITYRO0x100x00Activity
[3]INACTIVITYRO0x080x00Inactivity
[2]FREE_FALLRO0x040x00Free fall
[1]WATERMARKRO0x020x01FIFO watermark
[0]OVERRUNRO0x010x00FIFO overrun
DATA_FORMAT  @  0x31  —  6 fields
SELF_TEST[7]
SPI[6]
INT_INVERT[5]
—4
FULL_RES[3]
JUSTIFY[2]
RANGE[1:0]
BitsFieldAccessMaskResetDescription
[7]SELF_TESTRW0x800x00Apply a self-test force to the sensor
[6]SPIRW0x400x000 = 4-wire SPI, 1 = 3-wire SPI
[5]INT_INVERTRW0x200x000 = interrupts active high, 1 = active low
[3]FULL_RESRW0x080x001 = full resolution, 4 mg per LSB at every range. 0 = fixed 10-bit.
[2]JUSTIFYRW0x040x001 = left-justified (MSB) mode
[1:0]RANGERW0x030x00g range

DATA_FORMAT.RANGE values

ValueNameMeaning
0x00G_2+/-2 g (default)
0x01G_4+/-4 g
0x02G_8+/-8 g
0x03G_16+/-16 g
FIFO_CTL  @  0x38  —  3 fields
FIFO_MODE[7:6]
TRIGGER[5]
SAMPLES[4:0]
BitsFieldAccessMaskResetDescription
[7:6]FIFO_MODERW0xC00x00FIFO mode
[5]TRIGGERRW0x200x000 = trigger on INT1, 1 = trigger on INT2
[4:0]SAMPLESRW0x1F0x00Watermark sample count

FIFO_CTL.FIFO_MODE values

ValueNameMeaning
0x00BYPASSFIFO bypassed (default)
0x01FIFOCollect until full, then stop
0x02STREAMKeep the most recent 32 samples
0x03TRIGGERHold samples around a trigger event
FIFO_STATUS  @  0x39  —  2 fields
FIFO_TRIG[7]
—6
ENTRIES[5:0]
BitsFieldAccessMaskResetDescription
[7]FIFO_TRIGRO0x800x00A trigger event has occurred
[5:0]ENTRIESRO0x3F0x00Number of samples in the FIFO

Generated C header

What regforge gen ADXL345 writes for ACT_INACT_CTL:

/* ------------------------------------------------------------------------ */
/* ACT_INACT_CTL @ 0x27u  rw  8-bit  reset 0x00u */
/* Axis enables for activity and inactivity detection */
/* ------------------------------------------------------------------------ */

#define ADXL345_ACT_INACT_CTL                          0x27u
#define ADXL345_ACT_INACT_CTL_WIDTH                    8u
#define ADXL345_ACT_INACT_CTL_RESET                    0x00u

/*   ACT_AC_DC bits [7] rw reset 0x00u -- Activity: 0 = dc-coupled, 1 = ac-coupled */
#define ADXL345_ACT_INACT_CTL_ACT_AC_DC_SHIFT          7u
#define ADXL345_ACT_INACT_CTL_ACT_AC_DC_WIDTH          1u
#define ADXL345_ACT_INACT_CTL_ACT_AC_DC_MASK           0x80u
#define ADXL345_ACT_INACT_CTL_ACT_AC_DC_GET(reg)       (((uint8_t)(reg) & 0x80u) >> 7u)
#define ADXL345_ACT_INACT_CTL_ACT_AC_DC_SET(reg, val)  (((uint8_t)(reg) & (uint8_t)~0x80u) | (((uint8_t)(val) << 7u) & 0x80u))

/*   ACT_X_EN bits [6] rw reset 0x00u -- Enable X for activity */
#define ADXL345_ACT_INACT_CTL_ACT_X_EN_SHIFT           6u
#define ADXL345_ACT_INACT_CTL_ACT_X_EN_WIDTH           1u
#define ADXL345_ACT_INACT_CTL_ACT_X_EN_MASK            0x40u
#define ADXL345_ACT_INACT_CTL_ACT_X_EN_GET(reg)        (((uint8_t)(reg) & 0x40u) >> 6u)
#define ADXL345_ACT_INACT_CTL_ACT_X_EN_SET(reg, val)   (((uint8_t)(reg) & (uint8_t)~0x40u) | (((uint8_t)(val) << 6u) & 0x40u))

/*   ACT_Y_EN bits [5] rw reset 0x00u -- Enable Y for activity */
#define ADXL345_ACT_INACT_CTL_ACT_Y_EN_SHIFT           5u
#define ADXL345_ACT_INACT_CTL_ACT_Y_EN_WIDTH           1u
#define ADXL345_ACT_INACT_CTL_ACT_Y_EN_MASK            0x20u
#define ADXL345_ACT_INACT_CTL_ACT_Y_EN_GET(reg)        (((uint8_t)(reg) & 0x20u) >> 5u)
#define ADXL345_ACT_INACT_CTL_ACT_Y_EN_SET(reg, val)   (((uint8_t)(reg) & (uint8_t)~0x20u) | (((uint8_t)(val) << 5u) & 0x20u))

/*   ACT_Z_EN bits [4] rw reset 0x00u -- Enable Z for activity */
#define ADXL345_ACT_INACT_CTL_ACT_Z_EN_SHIFT           4u
#define ADXL345_ACT_INACT_CTL_ACT_Z_EN_WIDTH           1u
#define ADXL345_ACT_INACT_CTL_ACT_Z_EN_MASK            0x10u
#define ADXL345_ACT_INACT_CTL_ACT_Z_EN_GET(reg)        (((uint8_t)(reg) & 0x10u) >> 4u)
#define ADXL345_ACT_INACT_CTL_ACT_Z_EN_SET(reg, val)   (((uint8_t)(reg) & (uint8_t)~0x10u) | (((uint8_t)(val) << 4u) & 0x10u))

/*   INACT_AC_DC bits [3] rw reset 0x00u -- Inactivity: 0 = dc-coupled, 1 = ac-coupled */
#define ADXL345_ACT_INACT_CTL_INACT_AC_DC_SHIFT        3u
#define ADXL345_ACT_INACT_CTL_INACT_AC_DC_WIDTH        1u
#define ADXL345_ACT_INACT_CTL_INACT_AC_DC_MASK         0x08u
#define ADXL345_ACT_INACT_CTL_INACT_AC_DC_GET(reg)     (((uint8_t)(reg) & 0x08u) >> 3u)
#define ADXL345_ACT_INACT_CTL_INACT_AC_DC_SET(reg, val) (((uint8_t)(reg) & (uint8_t)~0x08u) | (((uint8_t)(val) << 3u) & 0x08u))

Compared with

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Source

Transcribed from Analog Devices ADXL345 datasheet (hand-transcribed) (hand-transcribed). Hand-authored seed entry, not machine-extracted. Check against Analog Devices ADXL345 datasheet before trusting it, then mark it verified.

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