INA226 register map

Bidirectional current and power monitor with alert and I2C — Texas Instruments

10 registers I2C I²C 0x40, 0x41, 0x42, 0x43, 0x44, 0x45, 0x46, 0x47, 0x48, 0x49, 0x4A, 0x4B, 0x4C, 0x4D, 0x4E, 0x4F 8-bit reg addresses 75% bit coverage not yet human-verified

I²C address conflict. On its default address(es) this part collides with ADS1115 (0x48, 0x49, 0x4A, 0x4B); INA219 (0x40, 0x41, 0x42, 0x43, 0x44, 0x45, 0x46, 0x47, 0x48, 0x49, 0x4A, 0x4B, 0x4C, 0x4D, 0x4E, 0x4F); PCA9685 (0x40, 0x41, 0x42, 0x43, 0x44, 0x45, 0x46, 0x47, 0x48, 0x49, 0x4A, 0x4B, 0x4C, 0x4D, 0x4E, 0x4F). You cannot put them on the same bus without changing a strap pin, using an I²C multiplexer, or moving one to a second bus. See the full address map.

Get it as a C header

pip install regforge
regforge gen INA226 --out ./src --driver --tests

Writes ina226_regs.h with every address, mask and shift below, a bus-agnostic driver skeleton, and a file of compile-time assertions that make your compiler check the bit arithmetic. No API key needed — this part ships inside the package.

Not yet human-verified. Transcribed and mechanically validated — no overlapping fields, no out-of-range bits, reset values consistent with their fields — but not yet checked line-by-line against the datasheet. Verifying it is a useful half hour.

Registers

Addr	Register	Access	Width	Reset	Description
0x00	CONFIG	RW	16	0x4127	Averaging, conversion times and operating mode
0x01	SHUNT_VOLTAGE	RO	16	—	Measured shunt voltage, two's complement, 2.5 uV per LSB
0x02	BUS_VOLTAGE	RO	16	—	Measured bus voltage, 1.25 mV per LSB
0x03	POWER	RO	16	0x0000	Calculated power. Reads zero until CALIBRATION has been written.
0x04	CURRENT	RO	16	0x0000	Calculated current, two's complement. Reads zero until CALIBRATION has been written.
0x05	CALIBRATION	RW	16	0x0000	Current and power scaling. Set from the shunt resistance and the maximum expected current.
0x06	MASK_ENABLE	RW	16	0x0000	Alert source selection and status flags
0x07	ALERT_LIMIT	RW	16	0x0000	Threshold compared against whichever alert source MASK_ENABLE selects
0xFE	MANUFACTURER_ID	RO	16	0x5449	Manufacturer ID. Reads 0x5449, which is 'TI' in ASCII.
0xFF	DIE_ID	RO	16	0x2260	Die ID and revision. Reads 0x2260.

Bit layouts

Drawn MSB-first, the way the datasheet draws them. [7:5] means shift 5, width 3, mask 0xE0 — this is the notation that costs people a day when they read it backwards.

CONFIG @ 0x00 — 5 fields

RST[15]

—14

—13

—12

AVG[11:9]

VBUSCT[8:6]

VSHCT[5:3]

MODE[2:0]

Bits	Field	Access	Mask	Reset	Description
[15]	RST	W1P	0x8000	0x00	Write 1 to reset every register to its default; self-clearing
[11:9]	AVG	RW	0x0E00	0x00	Averaging mode
[8:6]	VBUSCT	RW	0x01C0	0x04	Bus voltage conversion time
[5:3]	VSHCT	RW	0x0038	0x04	Shunt voltage conversion time
[2:0]	MODE	RW	0x0007	0x07	Operating mode

CONFIG.AVG values

Value	Name	Meaning
0x00	SAMPLES_1	1 sample (default)
0x01	SAMPLES_4	4 samples averaged
0x02	SAMPLES_16	16 samples averaged
0x03	SAMPLES_64	64 samples averaged
0x04	SAMPLES_128	128 samples averaged
0x05	SAMPLES_256	256 samples averaged
0x06	SAMPLES_512	512 samples averaged
0x07	SAMPLES_1024	1024 samples averaged

CONFIG.VBUSCT values

Value	Name	Meaning
0x00	US_140	140 us
0x01	US_204	204 us
0x02	US_332	332 us
0x03	US_588	588 us
0x04	US_1100	1.1 ms (default)
0x05	US_2116	2.116 ms
0x06	US_4156	4.156 ms
0x07	US_8244	8.244 ms

CONFIG.VSHCT values

Value	Name	Meaning
0x00	US_140	140 us
0x01	US_204	204 us
0x02	US_332	332 us
0x03	US_588	588 us
0x04	US_1100	1.1 ms (default)
0x05	US_2116	2.116 ms
0x06	US_4156	4.156 ms
0x07	US_8244	8.244 ms

CONFIG.MODE values

Value	Name	Meaning
0x00	POWER_DOWN	Power down
0x01	SHUNT_TRIGGERED	Shunt voltage, triggered
0x02	BUS_TRIGGERED	Bus voltage, triggered
0x03	SHUNT_BUS_TRIGGERED	Shunt and bus, triggered
0x04	POWER_DOWN_ALT	Power down (alternate encoding)
0x05	SHUNT_CONTINUOUS	Shunt voltage, continuous
0x06	BUS_CONTINUOUS	Bus voltage, continuous
0x07	SHUNT_BUS_CONTINUOUS	Shunt and bus, continuous (default)

MASK_ENABLE @ 0x06 — 11 fields

SOL[15]

SUL[14]

BOL[13]

BUL[12]

POL[11]

CNVR[10]

—9

—8

—7

—6

—5

AFF[4]

CVRF[3]

OVF[2]

APOL[1]

LEN[0]

Bits	Field	Access	Mask	Reset	Description
[15]	SOL	RW	0x8000	0x00	Alert on shunt voltage over limit
[14]	SUL	RW	0x4000	0x00	Alert on shunt voltage under limit
[13]	BOL	RW	0x2000	0x00	Alert on bus voltage over limit
[12]	BUL	RW	0x1000	0x00	Alert on bus voltage under limit
[11]	POL	RW	0x0800	0x00	Alert on power over limit
[10]	CNVR	RW	0x0400	0x00	Alert on conversion ready
[4]	AFF	RO	0x0010	0x00	Alert function flag
[3]	CVRF	RO	0x0008	0x00	Conversion ready flag
[2]	OVF	RO	0x0004	0x00	Math overflow flag
[1]	APOL	RW	0x0002	0x00	Alert polarity. 0 = active low (default).
[0]	LEN	RW	0x0001	0x00	Alert latch enable

Generated C header

What regforge gen INA226 writes for MASK_ENABLE:

/* ------------------------------------------------------------------------ */
/* MASK_ENABLE @ 0x06u  rw  16-bit  reset 0x0000u */
/* Alert source selection and status flags */
/* ------------------------------------------------------------------------ */

#define INA226_MASK_ENABLE                             0x06u
#define INA226_MASK_ENABLE_WIDTH                       16u
#define INA226_MASK_ENABLE_RESET                       0x0000u

/*   SOL bits [15] rw reset 0x00u -- Alert on shunt voltage over limit */
#define INA226_MASK_ENABLE_SOL_SHIFT                   15u
#define INA226_MASK_ENABLE_SOL_WIDTH                   1u
#define INA226_MASK_ENABLE_SOL_MASK                    0x8000u
#define INA226_MASK_ENABLE_SOL_GET(reg)                (((uint16_t)(reg) & 0x8000u) >> 15u)
#define INA226_MASK_ENABLE_SOL_SET(reg, val)           (((uint16_t)(reg) & (uint16_t)~0x8000u) | (((uint16_t)(val) << 15u) & 0x8000u))

/*   SUL bits [14] rw reset 0x00u -- Alert on shunt voltage under limit */
#define INA226_MASK_ENABLE_SUL_SHIFT                   14u
#define INA226_MASK_ENABLE_SUL_WIDTH                   1u
#define INA226_MASK_ENABLE_SUL_MASK                    0x4000u
#define INA226_MASK_ENABLE_SUL_GET(reg)                (((uint16_t)(reg) & 0x4000u) >> 14u)
#define INA226_MASK_ENABLE_SUL_SET(reg, val)           (((uint16_t)(reg) & (uint16_t)~0x4000u) | (((uint16_t)(val) << 14u) & 0x4000u))

/*   BOL bits [13] rw reset 0x00u -- Alert on bus voltage over limit */
#define INA226_MASK_ENABLE_BOL_SHIFT                   13u
#define INA226_MASK_ENABLE_BOL_WIDTH                   1u
#define INA226_MASK_ENABLE_BOL_MASK                    0x2000u
#define INA226_MASK_ENABLE_BOL_GET(reg)                (((uint16_t)(reg) & 0x2000u) >> 13u)
#define INA226_MASK_ENABLE_BOL_SET(reg, val)           (((uint16_t)(reg) & (uint16_t)~0x2000u) | (((uint16_t)(val) << 13u) & 0x2000u))

/*   BUL bits [12] rw reset 0x00u -- Alert on bus voltage under limit */
#define INA226_MASK_ENABLE_BUL_SHIFT                   12u
#define INA226_MASK_ENABLE_BUL_WIDTH                   1u
#define INA226_MASK_ENABLE_BUL_MASK                    0x1000u
#define INA226_MASK_ENABLE_BUL_GET(reg)                (((uint16_t)(reg) & 0x1000u) >> 12u)
#define INA226_MASK_ENABLE_BUL_SET(reg, val)           (((uint16_t)(reg) & (uint16_t)~0x1000u) | (((uint16_t)(val) << 12u) & 0x1000u))

/*   POL bits [11] rw reset 0x00u -- Alert on power over limit */
#define INA226_MASK_ENABLE_POL_SHIFT                   11u
#define INA226_MASK_ENABLE_POL_WIDTH                   1u
#define INA226_MASK_ENABLE_POL_MASK                    0x0800u
#define INA226_MASK_ENABLE_POL_GET(reg)                (((uint16_t)(reg) & 0x0800u) >> 11u)
#define INA226_MASK_ENABLE_POL_SET(reg, val)           (((uint16_t)(reg) & (uint16_t)~0x0800u) | (((uint16_t)(val) << 11u) & 0x0800u))

Compared with

INA226 vs INA219

Related parts

Source

Transcribed from TI INA226 datasheet (SBOS547) (hand-transcribed) (hand-transcribed). Hand-authored seed entry, not machine-extracted. Check against TI INA226 datasheet (SBOS547) before trusting it, then mark it verified.

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