All parts / ADS1115
ADS1115 register map
16-bit delta-sigma ADC with PGA, comparator and I2C interface — Texas Instruments
I²C address conflict. On its default address(es) this part collides with INA219 (0x48, 0x49, 0x4A, 0x4B); INA226 (0x48, 0x49, 0x4A, 0x4B); PCA9685 (0x48, 0x49, 0x4A, 0x4B). You cannot put them on the same bus without changing a strap pin, using an I²C multiplexer, or moving one to a second bus. See the full address map.
Get it as a C header
pip install regforge
regforge gen ADS1115 --out ./src --driver --testsWrites ads1115_regs.h with every address, mask and shift below, a bus-agnostic driver skeleton, and a file of compile-time assertions that make your compiler check the bit arithmetic. No API key needed — this part ships inside the package.
Not yet human-verified. Transcribed and mechanically validated — no overlapping fields, no out-of-range bits, reset values consistent with their fields — but not yet checked line-by-line against the datasheet. Verifying it is a useful half hour.
Registers
| Addr | Register | Access | Width | Reset | Description |
|---|---|---|---|---|---|
| 0x00 | CONVERSION | RO | 16 | 0x0000 | Last conversion result, two's complement, left-aligned |
| 0x01 | CONFIG | RW | 16 | 0x8583 | Operating mode, input multiplexer, PGA, data rate and comparator |
| 0x02 | LO_THRESH | RW | 16 | 0x8000 | Comparator low threshold, two's complement |
| 0x03 | HI_THRESH | RW | 16 | 0x7FFF | Comparator high threshold, two's complement |
Bit layouts
Drawn MSB-first, the way the datasheet draws them. [7:5] means shift 5, width 3, mask 0xE0 — this is the notation that costs people a day when they read it backwards.
CONFIG @ 0x01 — 9 fields
OS[15]
MUX[14:12]
PGA[11:9]
MODE[8]
DR[7:5]
COMP_MODE[4]
COMP_POL[3]
COMP_LAT[2]
COMP_QUE[1:0]
| Bits | Field | Access | Mask | Reset | Description |
|---|---|---|---|---|---|
| [15] | OS | RW | 0x8000 | 0x01 | Write 1 to start a single conversion; reads 0 while a conversion is running |
| [14:12] | MUX | RW | 0x7000 | 0x00 | Input multiplexer configuration |
| [11:9] | PGA | RW | 0x0E00 | 0x02 | Programmable gain amplifier setting |
| [8] | MODE | RW | 0x0100 | 0x01 | Conversion mode |
| [7:5] | DR | RW | 0x00E0 | 0x04 | Data rate |
| [4] | COMP_MODE | RW | 0x0010 | 0x00 | Comparator mode |
| [3] | COMP_POL | RW | 0x0008 | 0x00 | ALERT/RDY polarity |
| [2] | COMP_LAT | RW | 0x0004 | 0x00 | Latching comparator |
| [1:0] | COMP_QUE | RW | 0x0003 | 0x03 | Comparator queue and disable |
CONFIG.OS values
| Value | Name | Meaning |
|---|---|---|
| 0x00 | BUSY | Conversion in progress (on read) |
| 0x01 | START | Start a single conversion (on write) |
CONFIG.MUX values
| Value | Name | Meaning |
|---|---|---|
| 0x00 | AIN0_AIN1 | Differential AIN0 - AIN1 (default) |
| 0x01 | AIN0_AIN3 | Differential AIN0 - AIN3 |
| 0x02 | AIN1_AIN3 | Differential AIN1 - AIN3 |
| 0x03 | AIN2_AIN3 | Differential AIN2 - AIN3 |
| 0x04 | AIN0_GND | Single-ended AIN0 |
| 0x05 | AIN1_GND | Single-ended AIN1 |
| 0x06 | AIN2_GND | Single-ended AIN2 |
| 0x07 | AIN3_GND | Single-ended AIN3 |
CONFIG.PGA values
| Value | Name | Meaning |
|---|---|---|
| 0x00 | FSR_6_144V | Full-scale range +/-6.144 V |
| 0x01 | FSR_4_096V | Full-scale range +/-4.096 V |
| 0x02 | FSR_2_048V | Full-scale range +/-2.048 V (default) |
| 0x03 | FSR_1_024V | Full-scale range +/-1.024 V |
| 0x04 | FSR_0_512V | Full-scale range +/-0.512 V |
| 0x05 | FSR_0_256V | Full-scale range +/-0.256 V |
CONFIG.MODE values
| Value | Name | Meaning |
|---|---|---|
| 0x00 | CONTINUOUS | Continuous conversion |
| 0x01 | SINGLE_SHOT | Single-shot, power down between (default) |
CONFIG.DR values
| Value | Name | Meaning |
|---|---|---|
| 0x00 | SPS_8 | 8 samples per second |
| 0x01 | SPS_16 | 16 samples per second |
| 0x02 | SPS_32 | 32 samples per second |
| 0x03 | SPS_64 | 64 samples per second |
| 0x04 | SPS_128 | 128 samples per second (default) |
| 0x05 | SPS_250 | 250 samples per second |
| 0x06 | SPS_475 | 475 samples per second |
| 0x07 | SPS_860 | 860 samples per second |
CONFIG.COMP_MODE values
| Value | Name | Meaning |
|---|---|---|
| 0x00 | TRADITIONAL | Traditional comparator (default) |
| 0x01 | WINDOW | Window comparator |
CONFIG.COMP_POL values
| Value | Name | Meaning |
|---|---|---|
| 0x00 | ACTIVE_LOW | Active low (default) |
| 0x01 | ACTIVE_HIGH | Active high |
CONFIG.COMP_LAT values
| Value | Name | Meaning |
|---|---|---|
| 0x00 | NON_LATCHING | Non-latching (default) |
| 0x01 | LATCHING | Latching until read |
CONFIG.COMP_QUE values
| Value | Name | Meaning |
|---|---|---|
| 0x00 | ASSERT_AFTER_1 | Assert after one conversion |
| 0x01 | ASSERT_AFTER_2 | Assert after two conversions |
| 0x02 | ASSERT_AFTER_4 | Assert after four conversions |
| 0x03 | DISABLED | Comparator disabled, ALERT/RDY high-Z (default) |
Generated C header
What regforge gen ADS1115 writes for CONFIG:
/* ------------------------------------------------------------------------ */
/* CONFIG @ 0x01u rw 16-bit reset 0x8583u */
/* Operating mode, input multiplexer, PGA, data rate and comparator */
/* ------------------------------------------------------------------------ */
#define ADS1115_CONFIG 0x01u
#define ADS1115_CONFIG_WIDTH 16u
#define ADS1115_CONFIG_RESET 0x8583u
/* OS bits [15] rw reset 0x01u -- Write 1 to start a single conversion; reads 0 while a conversion is running */
#define ADS1115_CONFIG_OS_SHIFT 15u
#define ADS1115_CONFIG_OS_WIDTH 1u
#define ADS1115_CONFIG_OS_MASK 0x8000u
#define ADS1115_CONFIG_OS_GET(reg) (((uint16_t)(reg) & 0x8000u) >> 15u)
#define ADS1115_CONFIG_OS_SET(reg, val) (((uint16_t)(reg) & (uint16_t)~0x8000u) | (((uint16_t)(val) << 15u) & 0x8000u))
#define ADS1115_CONFIG_OS_BUSY 0x00u /* Conversion in progress (on read) */
#define ADS1115_CONFIG_OS_START 0x01u /* Start a single conversion (on write) */
/* MUX bits [14:12] rw reset 0x00u -- Input multiplexer configuration */
#define ADS1115_CONFIG_MUX_SHIFT 12u
#define ADS1115_CONFIG_MUX_WIDTH 3u
#define ADS1115_CONFIG_MUX_MASK 0x7000u
#define ADS1115_CONFIG_MUX_GET(reg) (((uint16_t)(reg) & 0x7000u) >> 12u)
#define ADS1115_CONFIG_MUX_SET(reg, val) (((uint16_t)(reg) & (uint16_t)~0x7000u) | (((uint16_t)(val) << 12u) & 0x7000u))
#define ADS1115_CONFIG_MUX_AIN0_AIN1 0x00u /* Differential AIN0 - AIN1 (default) */
#define ADS1115_CONFIG_MUX_AIN0_AIN3 0x01u /* Differential AIN0 - AIN3 */
#define ADS1115_CONFIG_MUX_AIN1_AIN3 0x02u /* Differential AIN1 - AIN3 */
#define ADS1115_CONFIG_MUX_AIN2_AIN3 0x03u /* Differential AIN2 - AIN3 */
#define ADS1115_CONFIG_MUX_AIN0_GND 0x04u /* Single-ended AIN0 */
#define ADS1115_CONFIG_MUX_AIN1_GND 0x05u /* Single-ended AIN1 */
#define ADS1115_CONFIG_MUX_AIN2_GND 0x06u /* Single-ended AIN2 */
#define ADS1115_CONFIG_MUX_AIN3_GND 0x07u /* Single-ended AIN3 */
/* PGA bits [11:9] rw reset 0x02u -- Programmable gain amplifier setting */
#define ADS1115_CONFIG_PGA_SHIFT 9u
#define ADS1115_CONFIG_PGA_WIDTH 3u
#define ADS1115_CONFIG_PGA_MASK 0x0E00u
#define ADS1115_CONFIG_PGA_GET(reg) (((uint16_t)(reg) & 0x0E00u) >> 9u)
#define ADS1115_CONFIG_PGA_SET(reg, val) (((uint16_t)(reg) & (uint16_t)~0x0E00u) | (((uint16_t)(val) << 9u) & 0x0E00u))
#define ADS1115_CONFIG_PGA_FSR_6_144V 0x00u /* Full-scale range +/-6.144 V */
#define ADS1115_CONFIG_PGA_FSR_4_096V 0x01u /* Full-scale range +/-4.096 V */
#define ADS1115_CONFIG_PGA_FSR_2_048V 0x02u /* Full-scale range +/-2.048 V (default) */
#define ADS1115_CONFIG_PGA_FSR_1_024V 0x03u /* Full-scale range +/-1.024 V */
#define ADS1115_CONFIG_PGA_FSR_0_512V 0x04u /* Full-scale range +/-0.512 V */Related parts
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Source
Transcribed from TI ADS1115 datasheet (SBAS444) (hand-transcribed) (hand-transcribed). Hand-authored seed entry, not machine-extracted. Check against TI ADS1115 datasheet (SBAS444) before trusting it, then mark it verified.