INA219 register map

High-side bidirectional current and power monitor with I2C — Texas Instruments

6 registers I2C I²C 0x40, 0x41, 0x42, 0x43, 0x44, 0x45, 0x46, 0x47, 0x48, 0x49, 0x4A, 0x4B, 0x4C, 0x4D, 0x4E, 0x4F 8-bit reg addresses 94% bit coverage not yet human-verified

I²C address conflict. On its default address(es) this part collides with ADS1115 (0x48, 0x49, 0x4A, 0x4B); INA226 (0x40, 0x41, 0x42, 0x43, 0x44, 0x45, 0x46, 0x47, 0x48, 0x49, 0x4A, 0x4B, 0x4C, 0x4D, 0x4E, 0x4F); PCA9685 (0x40, 0x41, 0x42, 0x43, 0x44, 0x45, 0x46, 0x47, 0x48, 0x49, 0x4A, 0x4B, 0x4C, 0x4D, 0x4E, 0x4F). You cannot put them on the same bus without changing a strap pin, using an I²C multiplexer, or moving one to a second bus. See the full address map.

Get it as a C header

pip install regforge
regforge gen INA219 --out ./src --driver --tests

Writes ina219_regs.h with every address, mask and shift below, a bus-agnostic driver skeleton, and a file of compile-time assertions that make your compiler check the bit arithmetic. No API key needed — this part ships inside the package.

Not yet human-verified. Transcribed and mechanically validated — no overlapping fields, no out-of-range bits, reset values consistent with their fields — but not yet checked line-by-line against the datasheet. Verifying it is a useful half hour.

Registers

Addr	Register	Access	Width	Reset	Description
0x00	CONFIG	RW	16	0x399F	Bus voltage range, PGA gain, ADC resolution/averaging and operating mode
0x01	SHUNT_VOLTAGE	RO	16	—	Measured shunt voltage, two's complement. LSB weight depends on the PG setting.
0x02	BUS_VOLTAGE	RO	16	—	Measured bus voltage, plus conversion-ready and overflow flags
0x03	POWER	RO	16	0x0000	Calculated power. Reads zero until CALIBRATION has been written.
0x04	CURRENT	RO	16	0x0000	Calculated current, two's complement. Reads zero until CALIBRATION has been written.
0x05	CALIBRATION	RW	16	0x0000	Current/power scaling. Bit 0 is not used; the value is effectively 15-bit.

Bit layouts

Drawn MSB-first, the way the datasheet draws them. [7:5] means shift 5, width 3, mask 0xE0 — this is the notation that costs people a day when they read it backwards.

CONFIG @ 0x00 — 6 fields

RST[15]

—14

BRNG[13]

PG[12:11]

BADC[10:7]

SADC[6:3]

MODE[2:0]

Bits	Field	Access	Mask	Reset	Description
[15]	RST	W1P	0x8000	0x00	Write 1 to reset all registers to their default values; self-clearing
[13]	BRNG	RW	0x2000	0x01	Bus voltage range
[12:11]	PG	RW	0x1800	0x03	Shunt voltage PGA gain and range
[10:7]	BADC	RW	0x0780	0x03	Bus ADC resolution and averaging
[6:3]	SADC	RW	0x0078	0x03	Shunt ADC resolution and averaging
[2:0]	MODE	RW	0x0007	0x07	Operating mode

CONFIG.BRNG values

Value	Name	Meaning
0x00	FSR_16V	16 V full scale
0x01	FSR_32V	32 V full scale (default)

CONFIG.PG values

Value	Name	Meaning
0x00	GAIN_1_40MV	Gain /1, +/-40 mV
0x01	GAIN_2_80MV	Gain /2, +/-80 mV
0x02	GAIN_4_160MV	Gain /4, +/-160 mV
0x03	GAIN_8_320MV	Gain /8, +/-320 mV (default)

CONFIG.BADC values

Value	Name	Meaning
0x00	RES_9BIT	9-bit, 84 us
0x01	RES_10BIT	10-bit, 148 us
0x02	RES_11BIT	11-bit, 276 us
0x03	RES_12BIT	12-bit, 532 us (default)
0x09	SAMPLES_2	12-bit, 2 samples averaged, 1.06 ms
0x0A	SAMPLES_4	12-bit, 4 samples averaged, 2.13 ms
0x0B	SAMPLES_8	12-bit, 8 samples averaged, 4.26 ms
0x0C	SAMPLES_16	12-bit, 16 samples averaged, 8.51 ms
0x0D	SAMPLES_32	12-bit, 32 samples averaged, 17.02 ms
0x0E	SAMPLES_64	12-bit, 64 samples averaged, 34.05 ms
0x0F	SAMPLES_128	12-bit, 128 samples averaged, 68.10 ms

CONFIG.SADC values

Value	Name	Meaning
0x00	RES_9BIT	9-bit, 84 us
0x01	RES_10BIT	10-bit, 148 us
0x02	RES_11BIT	11-bit, 276 us
0x03	RES_12BIT	12-bit, 532 us (default)
0x09	SAMPLES_2	12-bit, 2 samples averaged, 1.06 ms
0x0A	SAMPLES_4	12-bit, 4 samples averaged, 2.13 ms
0x0B	SAMPLES_8	12-bit, 8 samples averaged, 4.26 ms
0x0C	SAMPLES_16	12-bit, 16 samples averaged, 8.51 ms
0x0D	SAMPLES_32	12-bit, 32 samples averaged, 17.02 ms
0x0E	SAMPLES_64	12-bit, 64 samples averaged, 34.05 ms
0x0F	SAMPLES_128	12-bit, 128 samples averaged, 68.10 ms

CONFIG.MODE values

Value	Name	Meaning
0x00	POWER_DOWN	Power down
0x01	SHUNT_TRIGGERED	Shunt voltage, triggered
0x02	BUS_TRIGGERED	Bus voltage, triggered
0x03	SHUNT_BUS_TRIGGERED	Shunt and bus, triggered
0x04	ADC_OFF	ADC off / disabled
0x05	SHUNT_CONTINUOUS	Shunt voltage, continuous
0x06	BUS_CONTINUOUS	Bus voltage, continuous
0x07	SHUNT_BUS_CONTINUOUS	Shunt and bus, continuous (default)

BUS_VOLTAGE @ 0x02 — 3 fields

BD[15:3]

—2

CNVR[1]

OVF[0]

Bits	Field	Access	Mask	Reset	Description
[15:3]	BD	RO	0xFFF8	—	Bus voltage data, 4 mV per LSB
[1]	CNVR	RO	0x0002	—	Conversion ready; cleared by reading the POWER register or writing CONFIG
[0]	OVF	RO	0x0001	—	Math overflow: the power or current calculation was out of range

Generated C header

What regforge gen INA219 writes for CONFIG:

/* ------------------------------------------------------------------------ */
/* CONFIG @ 0x00u  rw  16-bit  reset 0x399Fu */
/* Bus voltage range, PGA gain, ADC resolution/averaging and operating mode */
/* ------------------------------------------------------------------------ */

#define INA219_CONFIG                                  0x00u
#define INA219_CONFIG_WIDTH                            16u
#define INA219_CONFIG_RESET                            0x399Fu

/*   RST bits [15] w1p reset 0x00u -- Write 1 to reset all registers to their default values; self-clearing */
#define INA219_CONFIG_RST_SHIFT                        15u
#define INA219_CONFIG_RST_WIDTH                        1u
#define INA219_CONFIG_RST_MASK                         0x8000u
#define INA219_CONFIG_RST_GET(reg)                     (((uint16_t)(reg) & 0x8000u) >> 15u)
#define INA219_CONFIG_RST_SET(reg, val)                (((uint16_t)(reg) & (uint16_t)~0x8000u) | (((uint16_t)(val) << 15u) & 0x8000u))

/*   BRNG bits [13] rw reset 0x01u -- Bus voltage range */
#define INA219_CONFIG_BRNG_SHIFT                       13u
#define INA219_CONFIG_BRNG_WIDTH                       1u
#define INA219_CONFIG_BRNG_MASK                        0x2000u
#define INA219_CONFIG_BRNG_GET(reg)                    (((uint16_t)(reg) & 0x2000u) >> 13u)
#define INA219_CONFIG_BRNG_SET(reg, val)               (((uint16_t)(reg) & (uint16_t)~0x2000u) | (((uint16_t)(val) << 13u) & 0x2000u))
#define INA219_CONFIG_BRNG_FSR_16V                     0x00u  /* 16 V full scale */
#define INA219_CONFIG_BRNG_FSR_32V                     0x01u  /* 32 V full scale (default) */

/*   PG bits [12:11] rw reset 0x03u -- Shunt voltage PGA gain and range */
#define INA219_CONFIG_PG_SHIFT                         11u
#define INA219_CONFIG_PG_WIDTH                         2u
#define INA219_CONFIG_PG_MASK                          0x1800u
#define INA219_CONFIG_PG_GET(reg)                      (((uint16_t)(reg) & 0x1800u) >> 11u)
#define INA219_CONFIG_PG_SET(reg, val)                 (((uint16_t)(reg) & (uint16_t)~0x1800u) | (((uint16_t)(val) << 11u) & 0x1800u))
#define INA219_CONFIG_PG_GAIN_1_40MV                   0x00u  /* Gain /1, +/-40 mV */
#define INA219_CONFIG_PG_GAIN_2_80MV                   0x01u  /* Gain /2, +/-80 mV */
#define INA219_CONFIG_PG_GAIN_4_160MV                  0x02u  /* Gain /4, +/-160 mV */
#define INA219_CONFIG_PG_GAIN_8_320MV                  0x03u  /* Gain /8, +/-320 mV (default) */

/*   BADC bits [10:7] rw reset 0x03u -- Bus ADC resolution and averaging */
#define INA219_CONFIG_BADC_SHIFT                       7u
#define INA219_CONFIG_BADC_WIDTH                       4u
#define INA219_CONFIG_BADC_MASK                        0x0780u
#define INA219_CONFIG_BADC_GET(reg)                    (((uint16_t)(reg) & 0x0780u) >> 7u)
#define INA219_CONFIG_BADC_SET(reg, val)               (((uint16_t)(reg) & (uint16_t)~0x0780u) | (((uint16_t)(val) << 7u) & 0x0780u))
#define INA219_CONFIG_BADC_RES_9BIT                    0x00u  /* 9-bit, 84 us */
#define INA219_CONFIG_BADC_RES_10BIT                   0x01u  /* 10-bit, 148 us */

Compared with

INA219 vs INA226

Related parts

Source

Transcribed from TI INA219 datasheet (SBOS448) (hand-transcribed) (hand-transcribed). Hand-authored seed entry, not machine-extracted. Check against TI INA219 datasheet (SBOS448) before trusting it, then mark it verified.

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