MPU6050 register map

Six-axis MEMS gyroscope and accelerometer with I2C — InvenSense

25 registers I2C I²C 0x68, 0x69 8-bit reg addresses 68% bit coverage not yet human-verified

I²C address conflict. On its default address(es) this part collides with DS1307 (0x68); DS3231 (0x68); PCA9685 (0x68, 0x69). You cannot put them on the same bus without changing a strap pin, using an I²C multiplexer, or moving one to a second bus. See the full address map.

Get it as a C header

pip install regforge
regforge gen MPU6050 --out ./src --driver --tests

Writes mpu6050_regs.h with every address, mask and shift below, a bus-agnostic driver skeleton, and a file of compile-time assertions that make your compiler check the bit arithmetic. No API key needed — this part ships inside the package.

Not yet human-verified. Transcribed and mechanically validated — no overlapping fields, no out-of-range bits, reset values consistent with their fields — but not yet checked line-by-line against the datasheet. Verifying it is a useful half hour.

Registers

Addr	Register	Access	Width	Reset	Description
0x19	SMPLRT_DIV	RW	8	0x00	Sample rate divider. Sample rate = gyroscope output rate / (1 + SMPLRT_DIV).
0x1A	CONFIG	RW	8	0x00	External frame synchronisation and digital low-pass filter configuration
0x1B	GYRO_CONFIG	RW	8	0x00	Gyroscope self-test and full-scale range
0x1C	ACCEL_CONFIG	RW	8	0x00	Accelerometer self-test and full-scale range
0x23	FIFO_EN	RW	8	0x00	Selects which sensor measurements are loaded into the FIFO
0x37	INT_PIN_CFG	RW	8	0x00	INT pin behaviour and I2C bypass
0x38	INT_ENABLE	RW	8	0x00	Interrupt enables
0x3A	INT_STATUS	RO	8	0x00	Interrupt status. Cleared on read.
0x3B	ACCEL_XOUT_H	RO	8	—	Accelerometer X-axis measurement, high byte
0x3C	ACCEL_XOUT_L	RO	8	—	Accelerometer X-axis measurement, low byte
0x3D	ACCEL_YOUT_H	RO	8	—	Accelerometer Y-axis measurement, high byte
0x3E	ACCEL_YOUT_L	RO	8	—	Accelerometer Y-axis measurement, low byte
0x3F	ACCEL_ZOUT_H	RO	8	—	Accelerometer Z-axis measurement, high byte
0x40	ACCEL_ZOUT_L	RO	8	—	Accelerometer Z-axis measurement, low byte
0x41	TEMP_OUT_H	RO	8	—	Temperature measurement, high byte
0x42	TEMP_OUT_L	RO	8	—	Temperature measurement, low byte
0x43	GYRO_XOUT_H	RO	8	—	Gyroscope X-axis measurement, high byte
0x44	GYRO_XOUT_L	RO	8	—	Gyroscope X-axis measurement, low byte
0x45	GYRO_YOUT_H	RO	8	—	Gyroscope Y-axis measurement, high byte
0x46	GYRO_YOUT_L	RO	8	—	Gyroscope Y-axis measurement, low byte
0x47	GYRO_ZOUT_H	RO	8	—	Gyroscope Z-axis measurement, high byte
0x48	GYRO_ZOUT_L	RO	8	—	Gyroscope Z-axis measurement, low byte
0x6B	PWR_MGMT_1	RW	8	0x40	Power mode and clock source. Note the reset value: SLEEP is set, so the device must be woken before it will produce data.
0x6C	PWR_MGMT_2	RW	8	0x00	Low-power wake rate and per-axis standby
0x75	WHO_AM_I	RO	8	0x68	Device identity. Contains the upper six bits of the I2C address; reads 0x68.

Bit layouts

Drawn MSB-first, the way the datasheet draws them. [7:5] means shift 5, width 3, mask 0xE0 — this is the notation that costs people a day when they read it backwards.

CONFIG @ 0x1A — 2 fields

—7

—6

EXT_SYNC_SET[5:3]

DLPF_CFG[2:0]

Bits	Field	Access	Mask	Reset	Description
[5:3]	EXT_SYNC_SET	RW	0x38	0x00	FSYNC pin sampling configuration
[2:0]	DLPF_CFG	RW	0x07	0x00	Digital low-pass filter bandwidth

GYRO_CONFIG @ 0x1B — 4 fields

XG_ST[7]

YG_ST[6]

ZG_ST[5]

FS_SEL[4:3]

—2

—1

—0

Bits	Field	Access	Mask	Reset	Description
[7]	XG_ST	RW	0x80	0x00	X-axis gyro self-test
[6]	YG_ST	RW	0x40	0x00	Y-axis gyro self-test
[5]	ZG_ST	RW	0x20	0x00	Z-axis gyro self-test
[4:3]	FS_SEL	RW	0x18	0x00	Gyroscope full-scale range

GYRO_CONFIG.FS_SEL values

Value	Name	Meaning
0x00	DPS_250	+/-250 degrees per second
0x01	DPS_500	+/-500 degrees per second
0x02	DPS_1000	+/-1000 degrees per second
0x03	DPS_2000	+/-2000 degrees per second

ACCEL_CONFIG @ 0x1C — 4 fields

XA_ST[7]

YA_ST[6]

ZA_ST[5]

AFS_SEL[4:3]

—2

—1

—0

Bits	Field	Access	Mask	Reset	Description
[7]	XA_ST	RW	0x80	0x00	X-axis accelerometer self-test
[6]	YA_ST	RW	0x40	0x00	Y-axis accelerometer self-test
[5]	ZA_ST	RW	0x20	0x00	Z-axis accelerometer self-test
[4:3]	AFS_SEL	RW	0x18	0x00	Accelerometer full-scale range

ACCEL_CONFIG.AFS_SEL values

Value	Name	Meaning
0x00	G_2	+/-2 g
0x01	G_4	+/-4 g
0x02	G_8	+/-8 g
0x03	G_16	+/-16 g

FIFO_EN @ 0x23 — 5 fields

TEMP_FIFO_EN[7]

XG_FIFO_EN[6]

YG_FIFO_EN[5]

ZG_FIFO_EN[4]

ACCEL_FIFO_EN[3]

—2

—1

—0

Bits	Field	Access	Mask	Reset	Description
[7]	TEMP_FIFO_EN	RW	0x80	0x00	Queue TEMP_OUT to the FIFO
[6]	XG_FIFO_EN	RW	0x40	0x00	Queue GYRO_XOUT to the FIFO
[5]	YG_FIFO_EN	RW	0x20	0x00	Queue GYRO_YOUT to the FIFO
[4]	ZG_FIFO_EN	RW	0x10	0x00	Queue GYRO_ZOUT to the FIFO
[3]	ACCEL_FIFO_EN	RW	0x08	0x00	Queue all accelerometer output to the FIFO

INT_PIN_CFG @ 0x37 — 7 fields

INT_LEVEL[7]

INT_OPEN[6]

LATCH_INT_EN[5]

INT_RD_CLEAR[4]

FSYNC_INT_LEVEL[3]

FSYNC_INT_EN[2]

I2C_BYPASS_EN[1]

—0

Bits	Field	Access	Mask	Reset	Description
[7]	INT_LEVEL	RW	0x80	0x00	0 = active high, 1 = active low
[6]	INT_OPEN	RW	0x40	0x00	0 = push-pull, 1 = open drain
[5]	LATCH_INT_EN	RW	0x20	0x00	0 = 50 us pulse, 1 = latched until cleared
[4]	INT_RD_CLEAR	RW	0x10	0x00	1 = any read clears the interrupt status
[3]	FSYNC_INT_LEVEL	RW	0x08	0x00	FSYNC interrupt active level
[2]	FSYNC_INT_EN	RW	0x04	0x00	Enable the FSYNC pin as an interrupt source
[1]	I2C_BYPASS_EN	RW	0x02	0x00	Connect the auxiliary I2C bus to the main bus

INT_ENABLE @ 0x38 — 3 fields

—7

—6

—5

FIFO_OFLOW_EN[4]

I2C_MST_INT_EN[3]

—2

—1

DATA_RDY_EN[0]

Bits	Field	Access	Mask	Reset	Description
[4]	FIFO_OFLOW_EN	RW	0x10	0x00	Interrupt on FIFO overflow
[3]	I2C_MST_INT_EN	RW	0x08	0x00	Interrupt on I2C master events
[0]	DATA_RDY_EN	RW	0x01	0x00	Interrupt when new sensor data is available

INT_STATUS @ 0x3A — 3 fields

—7

—6

—5

FIFO_OFLOW_INT[4]

I2C_MST_INT[3]

—2

—1

DATA_RDY_INT[0]

Bits	Field	Access	Mask	Reset	Description
[4]	FIFO_OFLOW_INT	RO	0x10	0x00	FIFO overflow occurred
[3]	I2C_MST_INT	RO	0x08	0x00	I2C master interrupt
[0]	DATA_RDY_INT	RO	0x01	0x00	New sensor data is available

PWR_MGMT_1 @ 0x6B — 5 fields

DEVICE_RESET[7]

SLEEP[6]

CYCLE[5]

—4

TEMP_DIS[3]

CLKSEL[2:0]

Bits	Field	Access	Mask	Reset	Description
[7]	DEVICE_RESET	W1P	0x80	0x00	Write 1 to reset all registers; self-clearing
[6]	SLEEP	RW	0x40	0x01	Sleep mode. Set at reset -- clear it to start measuring.
[5]	CYCLE	RW	0x20	0x00	Cycle between sleep and a single sample at LP_WAKE_CTRL rate
[3]	TEMP_DIS	RW	0x08	0x00	Disable the temperature sensor
[2:0]	CLKSEL	RW	0x07	0x00	Clock source select

PWR_MGMT_1.CLKSEL values

Value	Name	Meaning
0x00	INTERNAL_8MHZ	Internal 8 MHz oscillator
0x01	PLL_X_GYRO	PLL with X-axis gyro reference (recommended)
0x02	PLL_Y_GYRO	PLL with Y-axis gyro reference
0x03	PLL_Z_GYRO	PLL with Z-axis gyro reference
0x04	PLL_EXT_32K	PLL with external 32.768 kHz reference
0x05	PLL_EXT_19M	PLL with external 19.2 MHz reference
0x07	STOP	Stops the clock and holds the timing generator in reset

PWR_MGMT_2 @ 0x6C — 7 fields

LP_WAKE_CTRL[7:6]

STBY_XA[5]

STBY_YA[4]

STBY_ZA[3]

STBY_XG[2]

STBY_YG[1]

STBY_ZG[0]

Bits	Field	Access	Mask	Reset	Description
[7:6]	LP_WAKE_CTRL	RW	0xC0	0x00	Wake-up frequency in accelerometer-only low-power mode
[5]	STBY_XA	RW	0x20	0x00	Put the X-axis accelerometer into standby
[4]	STBY_YA	RW	0x10	0x00	Put the Y-axis accelerometer into standby
[3]	STBY_ZA	RW	0x08	0x00	Put the Z-axis accelerometer into standby
[2]	STBY_XG	RW	0x04	0x00	Put the X-axis gyro into standby
[1]	STBY_YG	RW	0x02	0x00	Put the Y-axis gyro into standby
[0]	STBY_ZG	RW	0x01	0x00	Put the Z-axis gyro into standby

Generated C header

What regforge gen MPU6050 writes for INT_PIN_CFG:

/* ------------------------------------------------------------------------ */
/* INT_PIN_CFG @ 0x37u  rw  8-bit  reset 0x00u */
/* INT pin behaviour and I2C bypass */
/* ------------------------------------------------------------------------ */

#define MPU6050_INT_PIN_CFG                            0x37u
#define MPU6050_INT_PIN_CFG_WIDTH                      8u
#define MPU6050_INT_PIN_CFG_RESET                      0x00u

/*   INT_LEVEL bits [7] rw reset 0x00u -- 0 = active high, 1 = active low */
#define MPU6050_INT_PIN_CFG_INT_LEVEL_SHIFT            7u
#define MPU6050_INT_PIN_CFG_INT_LEVEL_WIDTH            1u
#define MPU6050_INT_PIN_CFG_INT_LEVEL_MASK             0x80u
#define MPU6050_INT_PIN_CFG_INT_LEVEL_GET(reg)         (((uint8_t)(reg) & 0x80u) >> 7u)
#define MPU6050_INT_PIN_CFG_INT_LEVEL_SET(reg, val)    (((uint8_t)(reg) & (uint8_t)~0x80u) | (((uint8_t)(val) << 7u) & 0x80u))

/*   INT_OPEN bits [6] rw reset 0x00u -- 0 = push-pull, 1 = open drain */
#define MPU6050_INT_PIN_CFG_INT_OPEN_SHIFT             6u
#define MPU6050_INT_PIN_CFG_INT_OPEN_WIDTH             1u
#define MPU6050_INT_PIN_CFG_INT_OPEN_MASK              0x40u
#define MPU6050_INT_PIN_CFG_INT_OPEN_GET(reg)          (((uint8_t)(reg) & 0x40u) >> 6u)
#define MPU6050_INT_PIN_CFG_INT_OPEN_SET(reg, val)     (((uint8_t)(reg) & (uint8_t)~0x40u) | (((uint8_t)(val) << 6u) & 0x40u))

/*   LATCH_INT_EN bits [5] rw reset 0x00u -- 0 = 50 us pulse, 1 = latched until cleared */
#define MPU6050_INT_PIN_CFG_LATCH_INT_EN_SHIFT         5u
#define MPU6050_INT_PIN_CFG_LATCH_INT_EN_WIDTH         1u
#define MPU6050_INT_PIN_CFG_LATCH_INT_EN_MASK          0x20u
#define MPU6050_INT_PIN_CFG_LATCH_INT_EN_GET(reg)      (((uint8_t)(reg) & 0x20u) >> 5u)
#define MPU6050_INT_PIN_CFG_LATCH_INT_EN_SET(reg, val) (((uint8_t)(reg) & (uint8_t)~0x20u) | (((uint8_t)(val) << 5u) & 0x20u))

/*   INT_RD_CLEAR bits [4] rw reset 0x00u -- 1 = any read clears the interrupt status */
#define MPU6050_INT_PIN_CFG_INT_RD_CLEAR_SHIFT         4u
#define MPU6050_INT_PIN_CFG_INT_RD_CLEAR_WIDTH         1u
#define MPU6050_INT_PIN_CFG_INT_RD_CLEAR_MASK          0x10u
#define MPU6050_INT_PIN_CFG_INT_RD_CLEAR_GET(reg)      (((uint8_t)(reg) & 0x10u) >> 4u)
#define MPU6050_INT_PIN_CFG_INT_RD_CLEAR_SET(reg, val) (((uint8_t)(reg) & (uint8_t)~0x10u) | (((uint8_t)(val) << 4u) & 0x10u))

/*   FSYNC_INT_LEVEL bits [3] rw reset 0x00u -- FSYNC interrupt active level */
#define MPU6050_INT_PIN_CFG_FSYNC_INT_LEVEL_SHIFT      3u
#define MPU6050_INT_PIN_CFG_FSYNC_INT_LEVEL_WIDTH      1u
#define MPU6050_INT_PIN_CFG_FSYNC_INT_LEVEL_MASK       0x08u
#define MPU6050_INT_PIN_CFG_FSYNC_INT_LEVEL_GET(reg)   (((uint8_t)(reg) & 0x08u) >> 3u)
#define MPU6050_INT_PIN_CFG_FSYNC_INT_LEVEL_SET(reg, val) (((uint8_t)(reg) & (uint8_t)~0x08u) | (((uint8_t)(val) << 3u) & 0x08u))

Related parts

Source

Transcribed from InvenSense MPU-6000/MPU-6050 Register Map and Descriptions (hand-transcribed) (hand-transcribed). Hand-authored seed entry, not machine-extracted. Check against InvenSense MPU-6000/MPU-6050 Register Map and Descriptions before trusting it, then mark it verified.

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